405 lines
12 KiB
C
405 lines
12 KiB
C
#ifndef __CLOCK_HW_H__
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#define __CLOCK_HW_H__
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#include "typedef.h"
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#define RC_EN(x) SFR(JL_CLOCK->CLK_CON0, 0, 1, x)
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#define RCH_EN(x) SFR(JL_CLOCK->CLK_CON0, 0, 1, x)
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//for MACRO - RCH_EN
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enum {
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RCH_EN_250K = 0,
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RCH_EN_16M,
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};
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#define OSC_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON0, 1, 3, x)
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//for MACRO - OSC_CLOCK_IN
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enum {
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OSC_CLOCK_IN_BT_OSC = 0,
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OSC_CLOCK_IN_BT_OSC_X2,
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OSC_CLOCK_IN_STD_24M,
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OSC_CLOCK_IN_RTC_OSC,
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OSC_CLOCK_IN_LRC_CLK,
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OSC_CLOCK_IN_PAT,
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};
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#define PLL_96M_SEL_END 6
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#define PLL_96M_SEL_GET() ((JL_CLOCK->CLK_CON0 >> 4) & 0xF)
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#define PLL_96M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 4, 4, x)
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enum {
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PLL_96M_SEL_NULL = 0,
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PLL_96M_SEL_7DIV2, //f5
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PLL_96M_SEL_5DIV2, //f4
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PLL_96M_SEL_4DIV2, //f3
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PLL_96M_SEL_3DIV2, //f2
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PLL_96M_SEL_1DIV1, //f1
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PLL1_96M_SEL_7DIV2, //f5
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PLL1_96M_SEL_5DIV2, //f4
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PLL1_96M_SEL_4DIV2, //f3
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PLL1_96M_SEL_3DIV2, //f2
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PLL1_96M_SEL_1DIV1, //f1
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};
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#define PLL_48M_SEL_GET() ((JL_CLOCK->CLK_CON0 & BIT(8)) >> 8)
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#define PLL_48M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 8, 1, x)
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enum {
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PLL_48M_SEL_DIV2 = 0,
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PLL_48M_SEL_DIV1,
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};
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#define STD_48M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 9, 1, x)
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#define PLL_48M_TO_STD_48M 0
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#define BTOSCX2_TO_STD_48M 1
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#define STD_48M_SEL_GET() ((JL_CLOCK->CLK_CON0 & BIT(9)) >> 9)
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#define STD_24M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 10, 1, x)
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#define STD_48M_DIV2_TO_STD_24M 0
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#define BTOSC_TO_STD_24M 1
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#define PLL_SYS_SEL(x) SFR(JL_CLOCK->CLK_CON1, 0, 4, x)
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#define PLL_SYS_SEL_GET() ((JL_CLOCK->CLK_CON1 & 0xF))
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#define PLL_SYS_SEL_END 6
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//for MACRO - PLL_SYS_SEL
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enum {
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PLL_SYS_SEL_NULL = 0,
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PLL_SYS_SEL_7DIV2, //f5
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PLL_SYS_SEL_5DIV2, //f4
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PLL_SYS_SEL_4DIV2, //f3
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PLL_SYS_SEL_3DIV2, //f2
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PLL_SYS_SEL_1DIV1, //f1
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PLL1_SYS_SEL_7DIV2, //f5
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PLL1_SYS_SEL_5DIV2, //f4
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PLL1_SYS_SEL_4DIV2, //f3
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PLL1_SYS_SEL_3DIV2, //f2
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PLL1_SYS_SEL_1DIV1, //f1
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};
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#define PLL_SYS_DIV(x) SFR(JL_CLOCK->CLK_CON1, 4, 4, x)
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//for MACRO - PLL_SYS_DIV
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enum {
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PLL_SYS_DIV1 = 0,
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PLL_SYS_DIV3,
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PLL_SYS_DIV5,
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PLL_SYS_DIV7,
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PLL_SYS_DIV1X2 = 4,
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PLL_SYS_DIV3X2,
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PLL_SYS_DIV5X2,
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PLL_SYS_DIV7X2,
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PLL_SYS_DIV1X4 = 8,
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PLL_SYS_DIV3X4,
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PLL_SYS_DIV5X4,
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PLL_SYS_DIV7X4,
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PLL_SYS_DIV1X8 = 12,
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PLL_SYS_DIV3X8,
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PLL_SYS_DIV5X8,
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PLL_SYS_DIV7X8,
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};
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#define MAIN_CLOCK_SEL(x) SFR(JL_CLOCK->CLK_CON1, 8, 3, x); \
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asm("csync")
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//for MACRO - CLOCK_IN
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enum {
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MAIN_CLOCK_IN_RC_250K = 0,
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MAIN_CLOCK_IN_PAT,
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MAIN_CLOCK_IN_RTC_OSC,
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MAIN_CLOCK_IN_RC,
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MAIN_CLOCK_IN_BTOSC,
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MAIN_CLOCK_IN_BTOSC_X2,
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MAIN_CLOCK_IN_PLL,
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MAIN_CLOCK_IN_RTOSC_L, //keep to fix make
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};
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#define SFR_MODE(x) SFR(JL_CLOCK->CLK_CON1, 11, 1, x)
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enum {
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SFR_CLOCK_IDLE = 0,
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SFR_CLOCK_ALWAYS_ON,
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};
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#define BT_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
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//for MACRO - BT_CLOCK_IN
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enum {
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BT_CLOCK_IN_PLL48M = 0,
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BT_CLOCK_IN_HSB,
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BT_CLOCK_IN_LSB,
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BT_CLOCK_IN_DISABLE,
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};
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#define PLL_ALNK0_SEL(x) SFR(JL_CLOCK->CLK_CON2, 0, 3, x)
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#define PLL_ALNK0_DIV(x) SFR(JL_CLOCK->CLK_CON2, 3, 2, x)
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#define PLL_ALNK_EN(x) SFR(JL_CLOCK->CLK_CON2, 6, 1, x)
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#define PLL_ALNK_SEL(x) SFR(JL_CLOCK->CLK_CON2, 7, 1, x)
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//for MACRO - PLL_ALNK_SEL
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enum {
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PLL_ALNK_192M_DIV17 = 0,
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PLL_ALNK_480M_DIV39,
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};
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#define USB_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 8, 2, x)
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//for MACRO - USB_CLOCK_IN
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enum {
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USB_CLOCK_IN_PLL48M = 0,
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USB_CLOCK_IN_OSC,
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USB_CLOCK_IN_LSB,
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USB_CLOCK_IN_DISABLE,
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};
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#define UART_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 10, 2, x)
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//for MACRO - UART_CLOCK_IN
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enum {
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UART_CLOCK_IN_PLL24M = 0,
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UART_CLOCK_IN_OSC,
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UART_CLOCK_IN_LSB,
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UART_CLOCK_IN_DISABLE,
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};
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#define PLL_FM_SEL(x) SFR(JL_CLOCK->CLK_CON2, 12, 2, x)
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//for MACRO - PLL_APC_SEL
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enum {
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PLL_APC_SEL_PLL192M = 0,
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PLL_APC_SEL_PLL137M,
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PLL_APC_SEL_PLL107M,
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PLL_APC_SEL_DISABLE,
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};
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#define PLL_FM_DIV(x) SFR(JL_CLOCK->CLK_CON2, 14, 4, x)
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//for MACRO - PLL_APC_DIV
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enum {
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PLL_FM_DIV1 = 0,
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PLL_FM_DIV3,
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PLL_FM_DIV5,
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PLL_FM_DIV7,
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PLL_FM_DIV1X2 = 4,
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PLL_FM_DIV3X2,
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PLL_FM_DIV5X2,
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PLL_FM_DIV7X2,
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PLL_FM_DIV1X4 = 8,
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PLL_FM_DIV3X4,
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PLL_FM_DIV5X4,
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PLL_FM_DIV7X4,
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PLL_FM_DIV1X8 = 12,
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PLL_FM_DIV3X8,
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PLL_FM_DIV5X8,
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PLL_FM_DIV7X8,
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};
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#define GPCNT_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 28, 4, x)
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//for MACRO - DAC_CLOCK_IN
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enum {
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GPCNT_CLOCK_IN_NULL = 0,
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GPCNT_CLOCK_IN_SRC,
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GPCNT_CLOCK_IN_ORG,
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GPCNT_CLOCK_IN_HSB,
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GPCNT_CLOCK_IN_XOSC_FSCK,
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GPCNT_CLOCK_IN_BTOSC_48M,
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GPCNT_CLOCK_IN_WL,
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GPCNT_CLOCK_IN_USB,
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GPCNT_CLOCK_IN_PMU_ANA,
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GPCNT_CLOCK_IN_VAD_VCON0,
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GPCNT_CLOCK_IN_VAD_VCOP0,
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GPCNT_CLOCK_IN_RC_16M,
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GPCNT_CLOCK_IN_P33_RC_250k,
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GPCNT_CLOCK_IN_LRC,
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GPCNT_CLOCK_IN_DPLL_OUT,
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GPCNT_CLOCK_IN_RTC_OSC,
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};
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#define PLL_IMD_SEL_GET( ) ((JL_CLOCK->CLK_CON3 >> 8) & 0xF)
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#define PLL_IMD_SEL(x) SFR(JL_CLOCK->CLK_CON3, 8, 4, x)
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#define PLL_IMD_DIV(x) SFR(JL_CLOCK->CLK_CON3, 12, 4, x)
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#define PLL_TDM_SEL_GET(x) ((JL_CLOCK->CLK_CON3 >> 24) & 0x7)
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#define PLL_TDM_SEL(x) SFR(JL_CLOCK->CLK_CON3, 24, 3, x)
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#define PLL_TDM_DIV(x) SFR(JL_CLOCK->CLK_CON3, 27, 2, x)
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#define PLL_EN(x) SFR(JL_PLL0->CON0, 0, 1, (x))
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#define PLL_REST(x) SFR(JL_PLL0->CON0, 1, 1, (x))
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#define PLL_MODE(x) SFR(JL_PLL0->CON0, 2, 1, (x))
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#define PLL_PFDS(x) SFR(JL_PLL0->CON0, 3, 2, (x))
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#define PLL_ICPS(x) SFR(JL_PLL0->CON0, 5, 3, (x))
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#define PLL_LPFR2(x) SFR(JL_PLL0->CON0, 8, 3, (x))
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#define PLL_IVCO(x) SFR(JL_PLL0->CON0, 11, 3, (x))
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#define PLL_LDO12A(x) SFR(JL_PLL0->CON0, 14, 3, (x))
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#define PLL_LDO12D(x) SFR(JL_PLL0->CON0, 17, 3, (x))
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#define PLL_LDO_BYPASS(x) SFR(JL_PLL0->CON0, 20, 1, (x))
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#define PLL_TSEL(x) SFR(JL_PLL0->CON0, 21, 2, x)
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#define PLL_TEST(x) SFR(JL_PLL0->CON0, 23, 1, x)
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#define PLL_VBG_TR(x) SFR(JL_PLL0->CON0, 27, 4, (x))
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//REFDS
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#define PLL_DIVn(x) SFR(JL_PLL0->CON1, 0, 7, x)
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#define PLL_REF_SEL0(x) SFR(JL_PLL0->CON1, 7, 2, x)
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//for MACRO - PLL_RSEL0
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enum {
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PLL_RSEL_RCLK = 0, //
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PLL_RSEL_RCH,
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PLL_RSEL_DPLL_CLK,
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PLL_RSEL_PAT_CLK,
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};
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#define PLL_REF_SEL1(x) SFR(JL_PLL0->CON1, 9, 1, x)
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//for MACRO - PLL_REF_SEL1
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enum {
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PLL_REF_SEL_BTOSC_DIFF = 0, //btosc_DIFF
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PLL_REF_SEL_RCLK,
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};
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#define PLL_DIVn_EN(x) SFR(JL_PLL0->CON1, 10, 2, x)
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//for MACRO - PLL_DIVn_EN
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enum {
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PLL_DIVn_EN_X2 = 0,
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PLL_DIVn_DIS_DIV1,
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PLL_DIVn_EN_DIVn,
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};
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#define PLL_FBDS(x) SFR(JL_PLL0->CON2, 0, 12, x)
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#define PLL_CLK_1DIV1_OE(x) SFR(JL_PLL0->CON3, 0, 1, x) //f1
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#define PLL_CLK_3DIV2_OE(x) SFR(JL_PLL0->CON3, 1, 1, x) //f2
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#define PLL_CLK_4DIV2_OE(x) SFR(JL_PLL0->CON3, 2, 1, x) //f3
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#define PLL_CLK_5DIV2_OE(x) SFR(JL_PLL0->CON3, 3, 1, x) //f4
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#define PLL_CLK_7DIV2_OE(x) SFR(JL_PLL0->CON3, 4, 1, x) //f5
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#define PLL_CLK_EN(x) SFR(JL_PLL0->CON3, 9, 1, x)
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#define PLL1_EN(x) SFR(JL_PLL1->CON0, 0, 1, (x))
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#define PLL1_REST(x) SFR(JL_PLL1->CON0, 1, 1, (x))
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#define PLL1_MODE(x) SFR(JL_PLL1->CON0, 2, 1, (x))
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#define PLL1_PFDS(x) SFR(JL_PLL1->CON0, 3, 2, (x))
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#define PLL1_ICPS(x) SFR(JL_PLL1->CON0, 5, 3, (x))
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#define PLL1_LPFR2(x) SFR(JL_PLL1->CON0, 8, 3, (x))
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#define PLL1_IVCO(x) SFR(JL_PLL1->CON0, 11, 3, (x))
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#define PLL1_LDO12A(x) SFR(JL_PLL1->CON0, 14, 3, (x))
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#define PLL1_LDO12D(x) SFR(JL_PLL1->CON0, 17, 3, (x))
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#define PLL1_LDO_BYPASS(x) SFR(JL_PLL1->CON0, 20, 1, (x))
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#define PLL1_TSEL(x) SFR(JL_PLL1->CON0, 21, 2, x)
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#define PLL1_TEST(x) SFR(JL_PLL1->CON0, 23, 1, x)
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#define PLL1_VBG_TR(x) SFR(JL_PLL1->CON0, 27, 4, (x))
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#define PLL1_DIVn(x) SFR(JL_PLL1->CON1, 0, 7, x)
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#define PLL1_REF_SEL0(x) SFR(JL_PLL1->CON1, 7, 2, x)
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#define PLL1_REF_SEL1(x) SFR(JL_PLL1->CON1, 9, 1, x)
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#define PLL1_DIVn_EN(x) SFR(JL_PLL1->CON1, 10, 2, x)
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#define PLL1_FBDS(x) SFR(JL_PLL1->CON2, 0, 12, x)
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#define PLL1_CLK_1DIV1_OE(x) SFR(JL_PLL1->CON3, 0, 1, x) //f1
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#define PLL1_CLK_3DIV2_OE(x) SFR(JL_PLL1->CON3, 1, 1, x) //f2
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#define PLL1_CLK_4DIV2_OE(x) SFR(JL_PLL1->CON3, 2, 1, x) //f3
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#define PLL1_CLK_5DIV2_OE(x) SFR(JL_PLL1->CON3, 3, 1, x) //f4
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#define PLL1_CLK_7DIV2_OE(x) SFR(JL_PLL1->CON3, 4, 1, x) //f5
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#define PLL1_CLK_EN(x) SFR(JL_PLL1->CON3, 9, 1, x)
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#define HSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 0, 8, x)
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#define LSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 8, 3, x)
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#define SFC_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 12, 3, x)
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/********************************************************************************/
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#define GPCNT_EN(x) SFR(JL_GPCNT->CON, 0, 1, x)
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#define GPCNT_CSS(x) SFR(JL_GPCNT->CON, 1, 3, x)
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//for MACRO - GPCNT_CSS
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enum {
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GPCNT_CSS_LSB = 0,
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GPCNT_CSS_OSC,
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GPCNT_CSS_INPUT_CH2,
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GPCNT_CSS_INPUT_CH3,
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GPCNT_CSS_CLOCK_IN,
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GPCNT_CSS_RING,
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GPCNT_CSS_PLL,
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GPCNT_CSS_INTPUT_CH1,
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};
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#define GPCNT_CLR_PEND(x) SFR(JL_GPCNT->CON, 6, 1, x)
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#define GPCNT_GTS(x) SFR(JL_GPCNT->CON, 8, 4, x)
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#define GPCNT_GSS(x) SFR(JL_GPCNT->CON, 12, 3, x)
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//for MACRO - GPCNT_CSS
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enum {
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GPCNT_GSS_LSB = 0,
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GPCNT_GSS_OSC,
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GPCNT_GSS_INPUT_CH14, //iomap con1[27:24]
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GPCNT_GSS_INPUT_CH15, //iomap con1[31:28]
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GPCNT_GSS_CLOCK_IN, //CLK_CON2[31:28]
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GPCNT_GSS_RING,
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GPCNT_GSS_PLL,
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GPCNT_GSS_INPUT_CH13, //iomap con1[23:20]
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};
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//wla_con16 xosc
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#define XOSC_BGTR_10v_4(x) ((x&0xf)<<15)
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//wla_con8 xosc
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#define XOSC_EN_10v_1(x) ((x&0x1)<<0)
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#define XOSCLDO_PAS_10v_1(x) ((x&0x1)<<1)
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#define XOSCLDO_S_10v_3(x) ((x&0x7)<<2)
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#define XOSC_CPTEST_EN_10v_1(x) ((x&0x1)<<5)
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#define XOSC_HCS_10v_5(x) ((x&0x1f)<<6)
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#define XOSC_CLS_10v_4(x) ((x&0xf)<<11)
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#define XOSC_CRS_10v_4(x) ((x&0xf)<<15)
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#define XOSC_BT_HDS_10v_2(x) ((x&0x3)<<19)
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#define XOSC_ANATEST_EN_10v_1(x) ((x&0x1)<<21)
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#define XOSC_ANATEST_S_10v_3(x) ((x&0x7)<<22)
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#define XOSC_BT_OE_10v_1(x) ((x&0x1)<<25)
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#define XOSC_SYS1_OE_10v_1(x) ((x&0x1)<<26)
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#define XOSC_CORE48M_OE_10v_1(x) ((x&0x1)<<27)
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#define XOSC_CORE48M_S_10v_3(x) ((x&0x7)<<28)
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#define XOSC_FSCK_OE_10v_1(x) ((x&0x1)<<31)
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//wla_con9 xosc
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#define XOSC_FTCS_10v_3(x) ((x&0x7)<<0)
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#define XOSC_FTOE_10v_1(x) ((x&0x1)<<3)
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#define XOSC_FTIS_10v_5(x) ((x&0x1f)<<4)
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#define XOSC_CORE24M_OE_10v_1(x) ((x&0x1)<<9)
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#define XOSC_CMP_MODE_10v_1(x) ((x&0x1)<<10)
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#define XOSC_FTEN_10v_1(x) ((x&0x1)<<11)
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#define XOSC_PMU_HDS_10v_2(x) ((x&0x3)<<12)
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#define XOSC_PMU_OE_10v_1(x) ((x&0x1)<<14)
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#define XOSC_SYS1_HDS_10v_2(x) ((x&0x3)<<15)
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#define XOSC_DAC_HDS_10v_2(x) ((x&0x3)<<17)
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#define XOSC_DAC_OE_10v_1(x) ((x&0x1)<<19)
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#define XOSC_LFSREN_10v_1(x) ((x&0x1)<<20)
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//wla_con10
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//PLL
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#define XOSC_ADET_EN_10v_1(x) ((x&0x1)<<0)
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#define XOSC_ADET_S_10v_2(x) ((x&0x3)<<1)
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#define XOSC_VAD_DIVS_10v_4(x) ((x&0xf)<<3)
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#define XOSC_SYS0_HDS_10v_2(x) ((x&0x3)<<7)
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#define XOSC_SYS0_OE_10v_1(x) ((x&0x1)<<9)
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#define XOSC_VAD_HDS_10v_2(x) ((x&0x3)<<10)
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#define XOSC_VAD_OE_10v_1(x) ((x&0x1)<<12)
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//wla_con21
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#define WLA_RD_MUX_4(x) ((x&0xf)<<0)
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//wla_con30
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#define XOSC_ADET_GET_RESULT() ((JL_WLA->WLA_CON30 >> 4) & 1)
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//CORE
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#define ROM_MULTI_CYCLE(x) SFR(JL_CMNG->CON0,3,2,(x))
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#endif
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