/**
******************************************************************************
* @file py32f040x8.h
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for PY32F040 devices.
* @version v1.0.1
*
******************************************************************************
* @attention
*
* © Copyright (c) 2023 Puya Semiconductor Co.
* All rights reserved.
*
* This software component is licensed by Puya under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
* @attention
*
* © Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup py32f040x8
* @{
*/
#ifndef __PY32F040X8_H
#define __PY32F040X8_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
#define __MPU_PRESENT 0 /*!< PY32F040 do not provide MPU */
#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 2 /*!< PY32F040 uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief PY32F040 Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
/*!< Interrupt Number Definition */
typedef enum
{
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** PY32F0 specific Interrupt Numbers *********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */
RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 */
FLASH_IRQn = 3, /*!< FLASH global Interrupt */
RCC_IRQn = 4, /*!< RCC global Interrupts */
EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
LCD_IRQn = 8, /*!< LCD global Interrupt */
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, 5, 6, 7 Interrupts */
ADC_COMP_IRQn = 12, /*!< ADC&COMP Interrupts */
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
TIM6_LPTIM1_IRQn = 17, /*!< TIM6, LPTIM1 global Interrupts */
TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 global Interrupt */
I2C2_IRQn = 24, /*!< I2C2 global Interrupt */
SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
USART1_IRQn = 27, /*!< USART1 global Interrupt */
USART2_IRQn = 28, /*!< USART2 global Interrupt */
USART3_4_IRQn = 29, /*!< USART3, 4 global Interrupts */
} IRQn_Type;
/**
* @}
*/
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_py32f0xx.h" /* PY32F0xx System Header */
#include
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief ADC Registers
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC desc SR, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC desc CR1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC desc CR2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC desc SMPR1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC desc SMPR2, Address offset: 0x10 */
__IO uint32_t SMPR3; /*!< ADC desc SMPR3, Address offset: 0x14 */
__IO uint32_t JOFR1; /*!< ADC desc JOFR1, Address offset: 0x18 */
__IO uint32_t JOFR2; /*!< ADC desc JOFR2, Address offset: 0x1C */
__IO uint32_t JOFR3; /*!< ADC desc JOFR3, Address offset: 0x20 */
__IO uint32_t JOFR4; /*!< ADC desc JOFR4, Address offset: 0x24 */
__IO uint32_t HTR; /*!< ADC desc HTR, Address offset: 0x28 */
__IO uint32_t LTR; /*!< ADC desc LTR, Address offset: 0x2C */
__IO uint32_t SQR1; /*!< ADC desc SQR1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC desc SQR2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC desc SQR3, Address offset: 0x38 */
__IO uint32_t JSQR; /*!< ADC desc JSQR, Address offset: 0x3C */
__IO uint32_t JDR1; /*!< ADC desc JDR1, Address offset: 0x40 */
__IO uint32_t JDR2; /*!< ADC desc JDR2, Address offset: 0x44 */
__IO uint32_t JDR3; /*!< ADC desc JDR3, Address offset: 0x48 */
__IO uint32_t JDR4; /*!< ADC desc JDR4, Address offset: 0x4C */
__IO uint32_t DR; /*!< ADC desc DR, Address offset: 0x50 */
__IO uint32_t CCSR; /*!< ADC desc CCSR, Address offset: 0x54 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
uint32_t RESERVED[17];
__IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x50 */
} ADC_Common_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
__IO uint32_t FR; /*!< COMP filter register, Address offset: 0x04 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
__IO uint32_t FR_ODD;
uint32_t RESERVED[2]; /*Reserved*/
__IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
__IO uint32_t FR_EVEN;
} COMP_Common_TypeDef;
///**
//* @brief CTC Registers
//*/
//typedef struct
//{
// __IO uint32_t CTL0; /*!< CTC desc CTL0, Address offset: 0x00 */
// __IO uint32_t CTL1; /*!< CTC desc CTL1, Address offset: 0x04 */
// __IO uint32_t SR; /*!< CTC desc SR, Address offset: 0x08 */
// __IO uint32_t INTC; /*!< CTC desc INTC, Address offset: 0x0C */
//} CTC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
__IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
__IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
} DBGMCU_TypeDef;
/**
* @brief DIV Registers
*/
typedef struct
{
__IO uint32_t DEND; /*!< DIV desc DEND, Address offset: 0x00 */
__IO uint32_t SOR; /*!< DIV desc SOR, Address offset: 0x04 */
__IO uint32_t QUOT; /*!< DIV desc REMA, Address offset: 0x08 */
__IO uint32_t REMA; /*!< DIV desc QUOT, Address offset: 0x0C */
__IO uint32_t SIGN; /*!< DIV desc SIGN, Address offset: 0x10 */
__IO uint32_t STAT; /*!< DIV desc STAT, Address offset: 0x1C */
} DIV_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
/**
* @brief Asynch Interrupt/Event Controller (EXTI)
*/
typedef struct
{
__IO uint32_t RTSR; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
__IO uint32_t FTSR; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
__IO uint32_t SWIER; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
__IO uint32_t PR; /*!< EXTI Pending Register 1 Address offset: 0x0C */
uint32_t RESERVED1[20]; /*!< Reserved 1, Address offset: 0x10 -- 0x5C */
__IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, Address offset: 0x60 -- 0x6C */
uint32_t RESERVED2[4]; /*!< Reserved 2, Address offset: 0x70 -- 0x7C */
__IO uint32_t IMR; /*!< EXTI Interrupt Mask Register, Address offset: 0x80 */
__IO uint32_t EMR; /*!< EXTI Event Mask Register, Address offset: 0x84 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */
__IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
__IO uint32_t BORCR; /*!< FLASH BORCR address register, Address offset: 0x24 */
__IO uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x28 */
__IO uint32_t WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */
uint32_t RESERVED4[(0x90 - 0x2C) / 4 - 1]; /*!< RESERVED4, Address offset: 0x30-0x8C */
__IO uint32_t STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */
uint32_t RESERVED5[(0x100 - 0x90) / 4 - 1]; /*!< RESERVED5, Address offset: 0x94-0xFC */
__IO uint32_t TS0; /*!< FLASH TS0 register, Address offset: 0x100 */
__IO uint32_t TS1; /*!< FLASH TS1 register, Address offset: 0x104 */
__IO uint32_t TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */
__IO uint32_t TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */
__IO uint32_t TS3; /*!< FLASH TS3 register, Address offset: 0x110 */
__IO uint32_t PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */
__IO uint32_t SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */
__IO uint32_t PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */
__IO uint32_t PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */
} FLASH_TypeDef;
/**
* @brief Option Bytes
*/
typedef struct
{
__IO uint8_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
__IO uint8_t USER; /*!< FLASH option byte user options, Address offset: 0x01 */
__IO uint8_t nRDP; /*!< Complemented FLASH option byte Read protection, Address offset: 0x02 */
__IO uint8_t nUSER; /*!< Complemented FLASH option byte user options, Address offset: 0x03 */
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x04 */
uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x08 */
__IO uint16_t WRP; /*!< FLASH option byte write protection, Address offset: 0x0C */
__IO uint16_t nWRP; /*!< Complemented FLASH option byte write protection, Address offset: 0x0E */
} OB_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief I2C Registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C desc CR1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C desc CR2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C desc OAR1, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C desc OAR2, Address offset: 0x0C */
__IO uint32_t DR; /*!< I2C desc DR, Address offset: 0x10 */
__IO uint32_t SR1; /*!< I2C desc SR1, Address offset: 0x14 */
__IO uint32_t SR2; /*!< I2C desc SR2, Address offset: 0x18 */
__IO uint32_t CCR; /*!< I2C desc CCR, Address offset: 0x1C */
__IO uint32_t TRISE; /*!< I2C desc TRISE, Address offset: 0x20 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
} IWDG_TypeDef;
/**
* @brief LCD
*/
typedef struct
{
__IO uint32_t CR0; /*!< LCD desc CR0, Address offset: 0x00 */
__IO uint32_t CR1; /*!< LCD desc CR1, Address offset: 0x04 */
__IO uint32_t INTCLR; /*!< LCD desc INTCLR, Address offset: 0x08 */
__IO uint32_t POEN0; /*!< LCD desc POEN0, Address offset: 0x0C */
__IO uint32_t POEN1; /*!< LCD desc POEN1, Address offset: 0x10 */
__IO uint32_t RAM[16]; /*!< LCD desc RAM0~F, Address offset: 0x14-0x53 */
} LCD_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
} LPTIM_TypeDef;
/**
* @brief OPA Registers
*/
typedef struct
{
__IO uint32_t RESERVED1[0x30 / 4]; /*!< RESERVED1, Address offset: 0x0-0x2C */
__IO uint32_t CR0; /*!< OPA desc CR0, Address offset: 0x30 */
__IO uint32_t CR1; /*!< OPA desc CR1, Address offset: 0x34 */
__IO uint32_t CR2; /*!< OPA desc CR2, Address offset: 0x38 */
__IO uint32_t CR; /*!< OPA desc CR, Address offset: 0x3C */
} OPA_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x08-0x10 */
__IO uint32_t SR; /*!< PWR Power Status Register, Address offset: 0x14 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
__IO uint32_t ECSCR; /*!< RCC External clock source control register, Address offset: 0x10 */
__IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
__IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
__IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
__IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
__IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
__IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
__IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
__IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
__IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x44-0x50 */
__IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
__IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */
__IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
__IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
} RCC_TypeDef;
/**
* @brief RTC Registers
*/
typedef struct
{
__IO uint32_t CRH; /*!< RTC desc CRH, Address offset: 0x00 */
__IO uint32_t CRL; /*!< RTC desc CRL, Address offset: 0x04 */
__IO uint32_t PRLH; /*!< RTC desc PRLH, Address offset: 0x08 */
__IO uint32_t PRLL; /*!< RTC desc PRLL, Address offset: 0x0C */
__IO uint32_t DIVH; /*!< RTC desc DIVH, Address offset: 0x10 */
__IO uint32_t DIVL; /*!< RTC desc DIVL, Address offset: 0x14 */
__IO uint32_t CNTH; /*!< RTC desc CNTH, Address offset: 0x18 */
__IO uint32_t CNTL; /*!< RTC desc CNTL, Address offset: 0x1C */
__IO uint32_t ALRH; /*!< RTC desc ALRH, Address offset: 0x20 */
__IO uint32_t ALRL; /*!< RTC desc ALRL, Address offset: 0x24 */
uint32_t RESERVED1;
__IO uint32_t BKP_RTCCR; /*!< RTC desc BKP_RTCCR, Address offset: 0x2C */
} RTC_TypeDef;
/**
* @brief SPI Registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI desc CR1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI desc CR2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI desc SR, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI desc DR, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI desc CRCPR, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI desc RXCRCR, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI desc TXCRCR, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI desc I2SCFGR, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI desc I2SPR, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t CFGR1; /*!< SYSCFG desc CFGR1, Address offset: 0x00 */
__IO uint32_t CFGR2; /*!< SYSCFG desc CFGR2, Address offset: 0x04 */
__IO uint32_t CFGR3; /*!< SYSCFG desc CFGR3, Address offset: 0x08 */
__IO uint32_t CFGR4; /*!< SYSCFG desc CFGR4, Address offset: 0x0C */
__IO uint32_t PAENS; /*!< SYSCFG desc PAENS, Address offset: 0x10 */
__IO uint32_t PBENS; /*!< SYSCFG desc PBENS, Address offset: 0x14 */
__IO uint32_t PCENS; /*!< SYSCFG desc PCENS, Address offset: 0x18 */
__IO uint32_t PFENS; /*!< SYSCFG desc PFENS, Address offset: 0x1C */
__IO uint32_t EIIC; /*!< SYSCFG desc PEENS, Address offset: 0x20 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t SR; /*!< USART Status register , Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
#define FLASH_END (0x0800FFFFUL) /*!< FLASH end address */
#define FLASH_SIZE (FLASH_END - FLASH_BASE + 1)
#define FLASH_PAGE_SIZE 0x00000100U /*!< FLASH Page Size, 256 Bytes */
#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define FLASH_SECTOR_SIZE 0x00002000U /*!< FLASH Sector Size, 8192 Bytes */
#define FLASH_SECTOR_NB (FLASH_SIZE / FLASH_SECTOR_SIZE)
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define SRAM_END (0x20001FFFUL) /*!< SRAM end address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
/*!< Peripheral memory map */
#define APBPERIPH_BASE (PERIPH_BASE)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
/*!< APB peripherals */
#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
#define LCD_BASE (APBPERIPH_BASE + 0x00002400UL)
#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL)
#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
//#define CTC_BASE (APBPERIPH_BASE + 0x00006C00UL)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
#define COMP1_BASE (APBPERIPH_BASE + 0x00010200UL)
#define COMP2_BASE (APBPERIPH_BASE + 0x00010210UL)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
#define OPA_BASE (APBPERIPH_BASE + 0x00010300UL)
#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL)
#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
/*!< AHB peripherals */
#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
#define OB_BASE 0x1FFF3100UL /*!< FLASH Option Bytes base address */
#define FLASHSIZE_BASE 0x1FFF31FCUL /*!< FLASH Size register base address */
#define UID_BASE 0x1FFF3000UL /*!< Unique device ID register base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
#define DIV_BASE (AHBPERIPH_BASE + 0x00003800UL)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define USART4 ((USART_TypeDef *) USART4_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
//#define CTC ((CTC_TypeDef *) CTC_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define LPTIM ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
#define OPA ((OPA_TypeDef *) OPA_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define DIV ((DIV_TypeDef *) DIV_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/******************** Bits definition for ADC_SR register *******************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000080 */
#define ADC_SR_AWD ADC_SR_AWD_Msk
#define ADC_SR_EOC_Pos (1U)
#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000004 */
#define ADC_SR_EOC ADC_SR_EOC_Msk
#define ADC_SR_JEOC_Pos (2U)
#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
#define ADC_SR_JEOC ADC_SR_JEOC_Msk
#define ADC_SR_JSTRT_Pos (3U)
#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000004 */
#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
#define ADC_SR_STRT_Pos (4U)
#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000004 */
#define ADC_SR_STRT ADC_SR_STRT_Msk
#define ADC_SR_OVER_Pos (5U)
#define ADC_SR_OVER_Msk (0x1UL << ADC_SR_OVER_Pos) /*!< 0x00000004 */
#define ADC_SR_OVER ADC_SR_OVER_Msk
/*!< ADC_CR1 */
#define ADC_CR1_AWDCH_Pos (0U)
#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< AWDCH[4:0] bits (desc AWDCH) */
#define ADC_CR1_AWDCH_0 (0x1UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
#define ADC_CR1_AWDCH_1 (0x2UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
#define ADC_CR1_AWDCH_2 (0x4UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
#define ADC_CR1_AWDCH_3 (0x8UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
#define ADC_CR1_EOCIE_Pos (5U)
#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
#define ADC_CR1_AWDIE_Pos (6U)
#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< desc AWDIE */
#define ADC_CR1_JEOCIE_Pos (7U)
#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!< desc JEOCIE */
#define ADC_CR1_SCAN_Pos (8U)
#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< desc SCAN */
#define ADC_CR1_AWDSGL_Pos (9U)
#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< desc AWDSGL */
#define ADC_CR1_JAUTO_Pos (10U)
#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< desc JAUTO */
#define ADC_CR1_DISCEN_Pos (11U)
#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< desc DISCEN */
#define ADC_CR1_JDISCEN_Pos (12U)
#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< desc JDISCEN */
#define ADC_CR1_DISCNUM_Pos (13U)
#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< DISCNUM[15:13] bits (desc DISCNUM) */
#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
#define ADC_CR1_JAWDEN_Pos (22U)
#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
#define ADC_CR1_AWDEN_Pos (23U)
#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
#define ADC_CR1_RESSEL_Pos (24U)
#define ADC_CR1_RESSEL_Msk (0x3UL << ADC_CR1_RESSEL_Pos) /*!< 0x03000000 */
#define ADC_CR1_RESSEL ADC_CR1_RESSEL_Msk
#define ADC_CR1_RESSEL_0 (0x1UL << ADC_CR1_RESSEL_Pos) /*!< 0x01000000 */
#define ADC_CR1_RESSEL_1 (0x2UL << ADC_CR1_RESSEL_Pos)
#define ADC_CR1_ADSTP_Pos (27U)
#define ADC_CR1_ADSTP_Msk (0x1UL << ADC_CR1_ADSTP_Pos) /*!< 0x08000000 */
#define ADC_CR1_ADSTP ADC_CR1_ADSTP_Msk
#define ADC_CR1_OVRIE_Pos (29U)
#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x20000000 */
#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
/*!< ADC_CR2 */
#define ADC_CR2_ADON_Pos (0U)
#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< desc ADON */
#define ADC_CR2_CONT_Pos (1U)
#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< desc CONT */
#define ADC_CR2_CAL_Pos (2U)
#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< desc CAL */
//#define ADC_CR2_RSTCAL_Pos (3U)
//#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
//#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk
#define ADC_CR2_DMA_Pos (8U)
#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
#define ADC_CR2_DMA ADC_CR2_DMA_Msk
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< desc ALIGN */
#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< JEXTSEL[14:12] bits (desc JEXTSEL) */
#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
#define ADC_CR2_JEXTTRIG_Pos (15U)
#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< desc JEXTTRIG */
#define ADC_CR2_EXTSEL_Pos (17U)
#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< EXTSEL[19:17] bits (desc EXTSEL) */
#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
#define ADC_CR2_EXTTRIG_Pos (20U)
#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< desc EXTTRIG */
#define ADC_CR2_JSWSTART_Pos (21U)
#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< desc JSWSTART */
#define ADC_CR2_SWSTART_Pos (22U)
#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< desc SWSTART */
#define ADC_CR2_TSVREFE_Pos (23U)
#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk
#define ADC_CR2_VREFBUFFERE_Pos (25U)
#define ADC_CR2_VREFBUFFERE_Msk (0x1UL << ADC_CR2_VREFBUFFERE_Pos) /*!< 0x00800000 */
#define ADC_CR2_VREFBUFFERE ADC_CR2_VREFBUFFERE_Msk
#define ADC_CR2_VREFBUFFERSEL_Pos (26U)
#define ADC_CR2_VREFBUFFERSEL_Msk (0x3UL << ADC_CR2_VREFBUFFERSEL_Pos) /*!< 0x0C000000 */
#define ADC_CR2_VREFBUFFERSEL ADC_CR2_VREFBUFFERSEL_Msk
#define ADC_CR2_VREFBUFFERSEL_0 (0x1UL << ADC_CR2_VREFBUFFERSEL_Pos) /*!< 0x04000000 */
#define ADC_CR2_VREFBUFFERSEL_1 (0x2UL << ADC_CR2_VREFBUFFERSEL_Pos) /*!< 0x08000000 */
/*!< ADC_SMPR1 */
#define ADC_SMPR1_SMP20_Pos (0U)
#define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< SMP10[2:0] bits (desc SMP10) */
#define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP21_Pos (3U)
#define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< SMP11[5:3] bits (desc SMP11) */
#define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP22_Pos (6U)
#define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< SMP12[8:6] bits (desc SMP12) */
#define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP23_Pos (9U)
#define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< SMP13[11:9] bits (desc SMP13) */
#define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */
/*!< ADC_SMPR2 */
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< SMP0[2:0] bits (desc SMP0) */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< SMP0[2:0] bits (desc SMP0) */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< SMP0[2:0] bits (desc SMP0) */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< SMP0[2:0] bits (desc SMP0) */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< SMP0[2:0] bits (desc SMP0) */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
#define ADC_SMPR2_SMP19_Pos (27U)
#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
/*!< ADC_SMPR3 */
#define ADC_SMPR3_SMP0_Pos (0U)
#define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos)
#define ADC_SMPR3_SMP1_Pos (3U)
#define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos)
#define ADC_SMPR3_SMP2_Pos (6U)
#define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos)
#define ADC_SMPR3_SMP3_Pos (9U)
#define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos)
#define ADC_SMPR3_SMP4_Pos (12U)
#define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos)
#define ADC_SMPR3_SMP5_Pos (15U)
#define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos)
#define ADC_SMPR3_SMP6_Pos (18U)
#define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos)
#define ADC_SMPR3_SMP7_Pos (21U)
#define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos)
#define ADC_SMPR3_SMP8_Pos (24U)
#define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos)
#define ADC_SMPR3_SMP9_Pos (27U)
#define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< SMP15[17:15] bits (desc SMP15) */
#define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos)
/*!< ADC_JOFR1 */
#define ADC_JOFR1_JOFFSET1_Pos (0U)
#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< JOFFSET1[11:0] bits (desc JOFFSET1) */
/*!< ADC_JOFR2 */
#define ADC_JOFR2_JOFFSET2_Pos (0U)
#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< JOFFSET2[11:0] bits (desc JOFFSET2) */
/*!< ADC_JOFR3 */
#define ADC_JOFR3_JOFFSET3_Pos (0U)
#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< JOFFSET3[11:0] bits (desc JOFFSET3) */
/*!< ADC_JOFR4 */
#define ADC_JOFR4_JOFFSET4_Pos (0U)
#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< JOFFSET4[11:0] bits (desc JOFFSET4) */
/*!< ADC_HTR */
#define ADC_HTR_HT_Pos (0U)
#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< HT[11:0] bits (desc HT) */
/*!< ADC_LTR */
#define ADC_LTR_LT_Pos (0U)
#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
#define ADC_LTR_LT ADC_LTR_LT_Msk
/*!< ADC_SQR1 */
#define ADC_SQR1_SQ13_Pos (0U)
#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< SQ13[4:0] bits (desc SQ13) */
#define ADC_SQR1_SQ13_0 (0x1UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
#define ADC_SQR1_SQ13_1 (0x2UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
#define ADC_SQR1_SQ13_2 (0x4UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
#define ADC_SQR1_SQ13_3 (0x8UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
#define ADC_SQR1_SQ14_Pos (5U)
#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< SQ14[9:5] bits (desc SQ14) */
#define ADC_SQR1_SQ14_0 (0x1UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
#define ADC_SQR1_SQ14_1 (0x2UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ14_2 (0x4UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ14_3 (0x8UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ15_Pos (10U)
#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< SQ15[14:10] bits (desc SQ15) */
#define ADC_SQR1_SQ15_0 (0x1UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ15_1 (0x2UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
#define ADC_SQR1_SQ15_2 (0x4UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ15_3 (0x8UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ16_Pos (15U)
#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< SQ16[19:15] bits (desc SQ16) */
#define ADC_SQR1_SQ16_0 (0x1UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ16_1 (0x2UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ16_2 (0x4UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
#define ADC_SQR1_SQ16_3 (0x8UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
#define ADC_SQR1_L_Pos (20U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< L[23:20] bits (desc L) */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
/*!< ADC_SQR2 */
#define ADC_SQR2_SQ7_Pos (0U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< SQ7[4:0] bits (desc SQ7) */
#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ8_Pos (5U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< SQ8[9:5] bits (desc SQ8) */
#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ9_Pos (10U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< SQ9[14:10] bits (desc SQ9) */
#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ10_Pos (15U)
#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< SQ10[19:15] bits (desc SQ10) */
#define ADC_SQR2_SQ10_0 (0x1UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ10_1 (0x2UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ10_2 (0x4UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
#define ADC_SQR2_SQ10_3 (0x8UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ11_Pos (20U)
#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< SQ11[24:20] bits (desc SQ11) */
#define ADC_SQR2_SQ11_0 (0x1UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ11_1 (0x2UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ11_2 (0x4UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ11_3 (0x8UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ12_Pos (25U)
#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< SQ12[29:25] bits (desc SQ12) */
#define ADC_SQR2_SQ12_0 (0x1UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ12_1 (0x2UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ12_2 (0x4UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ12_3 (0x8UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
/*!< ADC_SQR3 */
#define ADC_SQR3_SQ1_Pos (0U)
#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< SQ1[4:0] bits (desc SQ1) */
#define ADC_SQR3_SQ1_0 (0x1UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ1_1 (0x2UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ1_2 (0x4UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ1_3 (0x8UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ2_Pos (5U)
#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< SQ2[9:5] bits (desc SQ2) */
#define ADC_SQR3_SQ2_0 (0x1UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
#define ADC_SQR3_SQ2_1 (0x2UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ2_2 (0x4UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ2_3 (0x8UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ3_Pos (10U)
#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< SQ3[14:10] bits (desc SQ3) */
#define ADC_SQR3_SQ3_0 (0x1UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ3_1 (0x2UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
#define ADC_SQR3_SQ3_2 (0x4UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ3_3 (0x8UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ4_Pos (15U)
#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< SQ4[19:15] bits (desc SQ4) */
#define ADC_SQR3_SQ4_0 (0x1UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ4_1 (0x2UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ4_2 (0x4UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
#define ADC_SQR3_SQ4_3 (0x8UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
#define ADC_SQR3_SQ5_Pos (20U)
#define ADC_SQR3_SQ5_Msk (0x1UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
#define ADC_SQR3_SQ5_0 (0x1UL << ADC_SQR3_SQ5_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ5_1 (0x2UL << ADC_SQR3_SQ5_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ5_2 (0x4UL << ADC_SQR3_SQ5_Pos) /*!< 0x00020000 */
#define ADC_SQR3_SQ5_3 (0x8UL << ADC_SQR3_SQ5_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
#define ADC_SQR3_SQ6_Pos (25U)
#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< SQ6[29:25] bits (desc SQ6) */
#define ADC_SQR3_SQ6_0 (0x1UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ6_1 (0x2UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ6_2 (0x4UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ6_3 (0x8UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
/*!< ADC_JSQR */
#define ADC_JSQR_JSQ1_Pos (0U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< JSQ1[4:0] bits (desc JSQ1) */
#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JSQ2_Pos (5U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< JSQ2[9:5] bits (desc JSQ2) */
#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ3_Pos (10U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< JSQ3[14:10] bits (desc JSQ3) */
#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ4_Pos (15U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< JSQ4[19:15] bits (desc JSQ4) */
#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
#define ADC_JSQR_JL_Pos (20U)
#define ADC_JSQR_JL_Msk (0xFUL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< JL[21:20] bits (desc JL) */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JL_2 (0x4UL << ADC_JSQR_JL_Pos)
#define ADC_JSQR_JL_3 (0x8UL << ADC_JSQR_JL_Pos)
/*!< ADC_JDR1 */
#define ADC_JDR1_JDR1_Pos (0U)
#define ADC_JDR1_JDR1_Msk (0xFFFFUL << ADC_JDR1_JDR1_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDR1 ADC_JDR1_JDR1_Msk /*!< JDR1[15:0] bits (desc JDR1) */
/*!< ADC_JDR2 */
#define ADC_JDR2_JDR2_Pos (0U)
#define ADC_JDR2_JDR2_Msk (0xFFFFUL << ADC_JDR2_JDR2_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDR2 ADC_JDR2_JDR2_Msk /*!< JDR2[15:0] bits (desc JDR2) */
/*!< ADC_JDR3 */
#define ADC_JDR3_JDR3_Pos (0U)
#define ADC_JDR3_JDR3_Msk (0xFFFFUL << ADC_JDR3_JDR3_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDR3 ADC_JDR3_JDR3_Msk /*!< JDR3[15:0] bits (desc JDR3) */
/*!< ADC_JDR4 */
#define ADC_JDR4_JDR4_Pos (0U)
#define ADC_JDR4_JDR4_Msk (0xFFFFUL << ADC_JDR4_JDR4_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDR4 ADC_JDR4_JDR4_Msk
/*!< ADC_DR */
#define ADC_DR_DATA_Pos (0U)
#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_DATA ADC_DR_DATA_Msk
/*!< ADC_CCSR */
#define ADC_CCSR_CALSEL_Pos (11U)
#define ADC_CCSR_CALSEL_Msk (0x1UL << ADC_CCSR_CALSEL_Pos) /*!< 0x00000800 */
#define ADC_CCSR_CALSEL ADC_CCSR_CALSEL_Msk /*!< desc CALSEL */
#define ADC_CCSR_CALSMP_Pos (12U)
#define ADC_CCSR_CALSMP_Msk (0x3UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00003000 */
#define ADC_CCSR_CALSMP ADC_CCSR_CALSMP_Msk /*!< CALSMP[13:12] bits (desc CALSMP) */
#define ADC_CCSR_CALSMP_0 (0x1UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00001000 */
#define ADC_CCSR_CALSMP_1 (0x2UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00002000 */
#define ADC_CCSR_CALBYP_Pos (14U)
#define ADC_CCSR_CALBYP_Msk (0x1UL << ADC_CCSR_CALBYP_Pos) /*!< 0x00004000 */
#define ADC_CCSR_CALBYP ADC_CCSR_CALBYP_Msk /*!< desc CALBYP */
#define ADC_CCSR_CALSET_Pos (15U)
#define ADC_CCSR_CALSET_Msk (0x1UL << ADC_CCSR_CALSET_Pos) /*!< 0x00008000 */
#define ADC_CCSR_CALSET ADC_CCSR_CALSET_Msk /*!< desc CALSET */
#define ADC_CCSR_OFFSUC_Pos (29U)
#define ADC_CCSR_OFFSUC_Msk (0x1UL << ADC_CCSR_OFFSUC_Pos) /*!< 0x20000000 */
#define ADC_CCSR_OFFSUC ADC_CCSR_OFFSUC_Msk /*!< desc OFFSUC */
#define ADC_CCSR_CAPSUC_Pos (30U)
#define ADC_CCSR_CAPSUC_Msk (0x1UL << ADC_CCSR_CAPSUC_Pos) /*!< 0x40000000 */
#define ADC_CCSR_CAPSUC ADC_CCSR_CAPSUC_Msk /*!< desc CAPSUC */
#define ADC_CCSR_CALON_Pos (31U)
#define ADC_CCSR_CALON_Msk (0x1UL << ADC_CCSR_CALON_Pos) /*!< 0x80000000 */
#define ADC_CCSR_CALON ADC_CCSR_CALON_Msk
/****************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/****************************************************************************/
/********************** Bit definition for COMP_CSR register **************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_COMP1_EN COMP_CSR_EN
#define COMP_CSR_COMP2_EN COMP_CSR_EN
#define COMP_CSR_INNSEL_Pos (2U)
#define COMP_CSR_INNSEL_Msk (0xFUL << COMP_CSR_INNSEL_Pos) /*!< 0x0000003C */
#define COMP_CSR_INNSEL COMP_CSR_INNSEL_Msk /*!< desc INNSEL */
#define COMP_CSR_INNSEL_0 (0x1UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000004 */
#define COMP_CSR_INNSEL_1 (0x2UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000008 */
#define COMP_CSR_INNSEL_2 (0x4UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INNSEL_3 (0x8UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INPSEL_Pos (6U)
#define COMP_CSR_INPSEL_Msk (0xFUL << COMP_CSR_INPSEL_Pos) /*!< 0x000003C0 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator plus minus selection */
#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL_3 (0x8UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */
#define COMP_CSR_WINMODE_Pos (11U)
#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */
#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis enable */
/*DEFINE FOR COMP1 CSR_HYST*/
#define COMP1_CSR_HYST_Pos (16U)
#define COMP1_CSR_HYST_Msk (0x1UL << COMP1_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP1_CSR_HYST COMP1_CSR_HYST_Msk /*!< Comparator1 hysteresis enable */
/*DEFINE FOR COMP2 CSR_HYST*/
#define COMP2_CSR_HYST_Pos (1U)
#define COMP2_CSR_HYST_Msk (0x1UL << COMP2_CSR_HYST_Pos) /*!< 0x00000002 */
#define COMP2_CSR_HYST COMP2_CSR_HYST_Msk /*!< Comparator2 hysteresis enable */
#define COMP_CSR_PWRMODE_Pos (18U)
#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */
#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */
#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */
#define COMP_CSR_VCDIV_Pos (20U)
#define COMP_CSR_VCDIV_Msk (0x3FUL << COMP_CSR_VCDIV_Pos) /*!< 0x03F00000 */
#define COMP_CSR_VCDIV COMP_CSR_VCDIV_Msk /*!< VCDIV[25:20] bits (desc VCDIV) */
#define COMP_CSR_VCDIV_0 (0x1UL << COMP_CSR_VCDIV_Pos) /*!< 0x00100000 */
#define COMP_CSR_VCDIV_1 (0x2UL << COMP_CSR_VCDIV_Pos) /*!< 0x00200000 */
#define COMP_CSR_VCDIV_2 (0x4UL << COMP_CSR_VCDIV_Pos) /*!< 0x00400000 */
#define COMP_CSR_VCDIV_3 (0x8UL << COMP_CSR_VCDIV_Pos) /*!< 0x00800000 */
#define COMP_CSR_VCDIV_4 (0x10UL << COMP_CSR_VCDIV_Pos) /*!< 0x01000000 */
#define COMP_CSR_VCDIV_5 (0x20UL << COMP_CSR_VCDIV_Pos) /*!< 0x02000000 */
#define COMP_CSR_VCDIV_EN_Pos (26U)
#define COMP_CSR_VCDIV_EN_Msk (0x1UL << COMP_CSR_VCDIV_EN_Pos) /*!< 0x04000000 */
#define COMP_CSR_VCDIV_EN COMP_CSR_VCDIV_EN_Msk /*!< desc VCDIV_EN */
#define COMP_CSR_VCSEL_Pos (27U)
#define COMP_CSR_VCSEL_Msk (0x1UL << COMP_CSR_VCSEL_Pos) /*!< 0x08000000 */
#define COMP_CSR_VCSEL COMP_CSR_VCSEL_Msk /*!< desc VCSEL */
#define COMP_CSR_COMP_OUT_Pos (30U)
#define COMP_CSR_COMP_OUT_Msk (0x1UL << COMP_CSR_COMP_OUT_Pos) /*!< 0x40000000 */
#define COMP_CSR_COMP_OUT COMP_CSR_COMP_OUT_Msk /*!< desc COMP_OUT */
/********************** Bit definition for COMP_FR register ***************/
#define COMP_FR_FLTEN_Pos (0U)
#define COMP_FR_FLTEN_Msk (0x1UL << COMP_FR_FLTEN_Pos) /*!< 0x00000001 */
#define COMP_FR_FLTEN COMP_FR_FLTEN_Msk /*!< Comparator filter enable */
#define COMP_FR_FLTCNT_Pos (16U)
#define COMP_FR_FLTCNT_Msk (0xFFFFUL << COMP_FR_FLTCNT_Pos) /*!< 0xFFFF0000 */
#define COMP_FR_FLTCNT COMP_FR_FLTCNT_Msk /*!< Comparator filter counter */
/****************************************************************************/
/* */
/* CRC calculation unit (CRC) */
/* */
/****************************************************************************/
/******************* Bit definition for CRC_DR register *******************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ******************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ******************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
///****************************************************************************/
///* */
///* Clock Triming Controller(CTC) */
///* */
///****************************************************************************/
///********************* Bits Define For Peripheral CTC *********************/
///*!< CTC_CTL0 */
//#define CTC_CTL0_CKOKIE_Pos (0U)
//#define CTC_CTL0_CKOKIE_Msk (0x1UL << CTC_CTL0_CKOKIE_Pos) /*!< 0x00000001 */
//#define CTC_CTL0_CKOKIE CTC_CTL0_CKOKIE_Msk /*!< desc CKOKIE */
//#define CTC_CTL0_CKWARNIE_Pos (1U)
//#define CTC_CTL0_CKWARNIE_Msk (0x1UL << CTC_CTL0_CKWARNIE_Pos) /*!< 0x00000002 */
//#define CTC_CTL0_CKWARNIE CTC_CTL0_CKWARNIE_Msk /*!< desc CKWARNIE */
//#define CTC_CTL0_ERRIE_Pos (2U)
//#define CTC_CTL0_ERRIE_Msk (0x1UL << CTC_CTL0_ERRIE_Pos) /*!< 0x00000004 */
//#define CTC_CTL0_ERRIE CTC_CTL0_ERRIE_Msk /*!< desc ERRIE */
//#define CTC_CTL0_EREFIE_Pos (3U)
//#define CTC_CTL0_EREFIE_Msk (0x1UL << CTC_CTL0_EREFIE_Pos) /*!< 0x00000008 */
//#define CTC_CTL0_EREFIE CTC_CTL0_EREFIE_Msk /*!< desc EREFIE */
//#define CTC_CTL0_CNTEN_Pos (5U)
//#define CTC_CTL0_CNTEN_Msk (0x1UL << CTC_CTL0_CNTEN_Pos) /*!< 0x00000020 */
//#define CTC_CTL0_CNTEN CTC_CTL0_CNTEN_Msk /*!< desc CNTEN */
//#define CTC_CTL0_AUTOTRIM_Pos (6U)
//#define CTC_CTL0_AUTOTRIM_Msk (0x1UL << CTC_CTL0_AUTOTRIM_Pos) /*!< 0x00000040 */
//#define CTC_CTL0_AUTOTRIM CTC_CTL0_AUTOTRIM_Msk /*!< desc AUTOTRIM */
//#define CTC_CTL0_SWREFPUL_Pos (7U)
//#define CTC_CTL0_SWREFPUL_Msk (0x1UL << CTC_CTL0_SWREFPUL_Pos) /*!< 0x00000080 */
//#define CTC_CTL0_SWREFPUL CTC_CTL0_SWREFPUL_Msk /*!< desc SWREFPUL */
//#define CTC_CTL0_TRIMVALUE_Pos (8U)
//#define CTC_CTL0_TRIMVALUE_Msk (0x3FUL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00003F00 */
//#define CTC_CTL0_TRIMVALUE CTC_CTL0_TRIMVALUE_Msk /*!< TRIMVALUE[13:8] bits (desc TRIMVALUE) */
//#define CTC_CTL0_TRIMVALUE_0 (0x1UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000100 */
//#define CTC_CTL0_TRIMVALUE_1 (0x2UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000200 */
//#define CTC_CTL0_TRIMVALUE_2 (0x4UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000400 */
//#define CTC_CTL0_TRIMVALUE_3 (0x8UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000800 */
//#define CTC_CTL0_TRIMVALUE_4 (0x10UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00001000 */
//#define CTC_CTL0_TRIMVALUE_5 (0x20UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00002000 */
//#define CTC_CTL0_TRIMVALUE_6 (0x40UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00004000 */
///*!< CTC_CTL1 */
//#define CTC_CTL1_RLVALUE_Pos (0U)
//#define CTC_CTL1_RLVALUE_Msk (0xFFFFUL << CTC_CTL1_RLVALUE_Pos) /*!< 0x0000FFFF */
//#define CTC_CTL1_RLVALUE CTC_CTL1_RLVALUE_Msk /*!< RLVALUE[15:0] bits (desc RLVALUE) */
//#define CTC_CTL1_CKLIM_Pos (16U)
//#define CTC_CTL1_CKLIM_Msk (0xFFUL << CTC_CTL1_CKLIM_Pos) /*!< 0x00FF0000 */
//#define CTC_CTL1_CKLIM CTC_CTL1_CKLIM_Msk /*!< CKLIM[23:16] bits (desc CKLIM) */
//#define CTC_CTL1_REFPSC_Pos (24U)
//#define CTC_CTL1_REFPSC_Msk (0x7UL << CTC_CTL1_REFPSC_Pos) /*!< 0x07000000 */
//#define CTC_CTL1_REFPSC CTC_CTL1_REFPSC_Msk /*!< REFPSC[26:24] bits (desc REFPSC) */
//#define CTC_CTL1_REFPSC_0 (0x1UL << CTC_CTL1_REFPSC_Pos) /*!< 0x01000000 */
//#define CTC_CTL1_REFPSC_1 (0x2UL << CTC_CTL1_REFPSC_Pos) /*!< 0x02000000 */
//#define CTC_CTL1_REFPSC_2 (0x4UL << CTC_CTL1_REFPSC_Pos) /*!< 0x04000000 */
//#define CTC_CTL1_REFSEL_Pos (28U)
//#define CTC_CTL1_REFSEL_Msk (0x3UL << CTC_CTL1_REFSEL_Pos) /*!< 0x30000000 */
//#define CTC_CTL1_REFSEL CTC_CTL1_REFSEL_Msk /*!< REFSEL[29:28] bits (desc REFSEL) */
//#define CTC_CTL1_REFSEL_0 (0x1UL << CTC_CTL1_REFSEL_Pos) /*!< 0x10000000 */
//#define CTC_CTL1_REFSEL_1 (0x2UL << CTC_CTL1_REFSEL_Pos) /*!< 0x20000000 */
//#define CTC_CTL1_REFPOL_Pos (31U)
//#define CTC_CTL1_REFPOL_Msk (0x1UL << CTC_CTL1_REFPOL_Pos) /*!< 0x80000000 */
//#define CTC_CTL1_REFPOL CTC_CTL1_REFPOL_Msk /*!< desc REFPOL */
///*!< CTC_SR */
//#define CTC_SR_CKOKIF_Pos (0U)
//#define CTC_SR_CKOKIF_Msk (0x1UL << CTC_SR_CKOKIF_Pos) /*!< 0x00000001 */
//#define CTC_SR_CKOKIF CTC_SR_CKOKIF_Msk /*!< desc CKOKIF */
//#define CTC_SR_CKWARNIF_Pos (1U)
//#define CTC_SR_CKWARNIF_Msk (0x1UL << CTC_SR_CKWARNIF_Pos) /*!< 0x00000002 */
//#define CTC_SR_CKWARNIF CTC_SR_CKWARNIF_Msk /*!< desc CKWARNIF */
//#define CTC_SR_ERRIF_Pos (2U)
//#define CTC_SR_ERRIF_Msk (0x1UL << CTC_SR_ERRIF_Pos) /*!< 0x00000004 */
//#define CTC_SR_ERRIF CTC_SR_ERRIF_Msk /*!< desc ERRIF */
//#define CTC_SR_EREFIF_Pos (3U)
//#define CTC_SR_EREFIF_Msk (0x1UL << CTC_SR_EREFIF_Pos) /*!< 0x00000008 */
//#define CTC_SR_EREFIF CTC_SR_EREFIF_Msk /*!< desc EREFIF */
//#define CTC_SR_CKERR_Pos (8U)
//#define CTC_SR_CKERR_Msk (0x1UL << CTC_SR_CKERR_Pos) /*!< 0x00000100 */
//#define CTC_SR_CKERR CTC_SR_CKERR_Msk /*!< desc CKERR */
//#define CTC_SR_REFMISS_Pos (9U)
//#define CTC_SR_REFMISS_Msk (0x1UL << CTC_SR_REFMISS_Pos) /*!< 0x00000200 */
//#define CTC_SR_REFMISS CTC_SR_REFMISS_Msk /*!< desc REFMISS */
//#define CTC_SR_TRIMERR_Pos (10U)
//#define CTC_SR_TRIMERR_Msk (0x1UL << CTC_SR_TRIMERR_Pos) /*!< 0x00000400 */
//#define CTC_SR_TRIMERR CTC_SR_TRIMERR_Msk /*!< desc TRIMERR */
//#define CTC_SR_REFDIR_Pos (15U)
//#define CTC_SR_REFDIR_Msk (0x1UL << CTC_SR_REFDIR_Pos) /*!< 0x00008000 */
//#define CTC_SR_REFDIR CTC_SR_REFDIR_Msk /*!< desc REFDIR */
//#define CTC_SR_REFCAP_Pos (16U)
//#define CTC_SR_REFCAP_Msk (0xFFFFUL << CTC_SR_REFCAP_Pos) /*!< 0xFFFF0000 */
//#define CTC_SR_REFCAP CTC_SR_REFCAP_Msk /*!< REFCAP[31:16] bits (desc REFCAP) */
///*!< CTC_INTC */
//#define CTC_INTC_CKOKIC_Pos (0U)
//#define CTC_INTC_CKOKIC_Msk (0x1UL << CTC_INTC_CKOKIC_Pos) /*!< 0x00000001 */
//#define CTC_INTC_CKOKIC CTC_INTC_CKOKIC_Msk /*!< desc CKOKIC */
//#define CTC_INTC_CKWARNIC_Pos (1U)
//#define CTC_INTC_CKWARNIC_Msk (0x1UL << CTC_INTC_CKWARNIC_Pos) /*!< 0x00000002 */
//#define CTC_INTC_CKWARNIC CTC_INTC_CKWARNIC_Msk /*!< desc CKWARNIC */
//#define CTC_INTC_ERRIC_Pos (2U)
//#define CTC_INTC_ERRIC_Msk (0x1UL << CTC_INTC_ERRIC_Pos) /*!< 0x00000004 */
//#define CTC_INTC_ERRIC CTC_INTC_ERRIC_Msk /*!< desc ERRIC */
//#define CTC_INTC_EREFIC_Pos (3U)
//#define CTC_INTC_EREFIC_Msk (0x1UL << CTC_INTC_EREFIC_Pos) /*!< 0x00000008 */
//#define CTC_INTC_EREFIC CTC_INTC_EREFIC_Msk /*!< desc EREFIC */
/****************************************************************************/
/* */
/* Debug MCU (DBGMCU) */
/* */
/****************************************************************************/
/******************** Bit definition for DBG_IDCODE register **************/
#define DBGMCU_IDCODE_REV_ID_Pos (0U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFFFFFF */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register ***************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
/******************** Bit definition for DBGMCU_APB_FZ1 register **********/
#define DBGMCU_APB_FZ1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB_FZ1_DBG_TIM2_STOP DBGMCU_APB_FZ1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB_FZ1_DBG_TIM3_STOP DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB_FZ1_DBG_TIM6_STOP DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB_FZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_APB_FZ1_DBG_TIM7_STOP DBGMCU_APB_FZ1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_APB_FZ1_DBG_RTC_STOP DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_APB_FZ1_DBG_WWDG_STOP DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_APB_FZ1_DBG_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Msk
#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Msk
#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos (31U)
#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk
#define DBGMCU_APB_FZ1_DBG_LPTIM1_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk
/******************** Bit definition for DBGMCU_APB_FZ2 register **********/
#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_APB_FZ2_DBG_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk
#define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos (15U)
#define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_APB_FZ2_DBG_TIM14_STOP DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk
#define DBGMCU_APB_FZ2_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
#define DBGMCU_APB_FZ2_DBG_TIM15_STOP DBGMCU_APB_FZ2_DBG_TIM15_STOP_Msk
#define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
#define DBGMCU_APB_FZ2_DBG_TIM16_STOP DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk
#define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
#define DBGMCU_APB_FZ2_DBG_TIM17_STOP DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk
/****************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/****************************************************************************/
/******************* Bit definition for DMA_ISR register ******************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *****************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ******************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *****************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ******************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ******************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/****************************************************************************/
/* */
/* External Interrupt/Event Controller (EXTI) */
/* */
/****************************************************************************/
/****************** Bit definition for EXTI_RTSR register *****************/
#define EXTI_RTSR_RT0_Pos (0U)
#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger configuration for input line 0 */
#define EXTI_RTSR_RT1_Pos (1U)
#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger configuration for input line 1 */
#define EXTI_RTSR_RT2_Pos (2U)
#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger configuration for input line 2 */
#define EXTI_RTSR_RT3_Pos (3U)
#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger configuration for input line 3 */
#define EXTI_RTSR_RT4_Pos (4U)
#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger configuration for input line 4 */
#define EXTI_RTSR_RT5_Pos (5U)
#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger configuration for input line 5 */
#define EXTI_RTSR_RT6_Pos (6U)
#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger configuration for input line 6 */
#define EXTI_RTSR_RT7_Pos (7U)
#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger configuration for input line 7 */
#define EXTI_RTSR_RT8_Pos (8U)
#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger configuration for input line 8 */
#define EXTI_RTSR_RT9_Pos (9U)
#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger configuration for input line 9 */
#define EXTI_RTSR_RT10_Pos (10U)
#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger configuration for input line 10 */
#define EXTI_RTSR_RT11_Pos (11U)
#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger configuration for input line 11 */
#define EXTI_RTSR_RT12_Pos (12U)
#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger configuration for input line 12 */
#define EXTI_RTSR_RT13_Pos (13U)
#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger configuration for input line 13 */
#define EXTI_RTSR_RT14_Pos (14U)
#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger configuration for input line 14 */
#define EXTI_RTSR_RT15_Pos (15U)
#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger configuration for input line 15 */
#define EXTI_RTSR_RT16_Pos (16U)
#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger configuration for input line 16 */
#define EXTI_RTSR_RT17_Pos (17U)
#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger configuration for input line 17 */
#define EXTI_RTSR_RT18_Pos (18U)
#define EXTI_RTSR_RT18_Msk (0x1UL << EXTI_RTSR_RT18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_RT18 EXTI_RTSR_RT18_Msk /*!< Rising trigger configuration for input line 18 */
#define EXTI_RTSR_RT20_Pos (20U)
#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger configuration for input line 20 */
/****************** Bit definition for EXTI_FTSR register *****************/
#define EXTI_FTSR_FT0_Pos (0U)
#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger configuration for input line 0 */
#define EXTI_FTSR_FT1_Pos (1U)
#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger configuration for input line 1 */
#define EXTI_FTSR_FT2_Pos (2U)
#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger configuration for input line 2 */
#define EXTI_FTSR_FT3_Pos (3U)
#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger configuration for input line 3 */
#define EXTI_FTSR_FT4_Pos (4U)
#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger configuration for input line 4 */
#define EXTI_FTSR_FT5_Pos (5U)
#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger configuration for input line 5 */
#define EXTI_FTSR_FT6_Pos (6U)
#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger configuration for input line 6 */
#define EXTI_FTSR_FT7_Pos (7U)
#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger configuration for input line 7 */
#define EXTI_FTSR_FT8_Pos (8U)
#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger configuration for input line 8 */
#define EXTI_FTSR_FT9_Pos (9U)
#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger configuration for input line 9 */
#define EXTI_FTSR_FT10_Pos (10U)
#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger configuration for input line 10 */
#define EXTI_FTSR_FT11_Pos (11U)
#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger configuration for input line 11 */
#define EXTI_FTSR_FT12_Pos (12U)
#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger configuration for input line 12 */
#define EXTI_FTSR_FT13_Pos (13U)
#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger configuration for input line 13 */
#define EXTI_FTSR_FT14_Pos (14U)
#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger configuration for input line 14 */
#define EXTI_FTSR_FT15_Pos (15U)
#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger configuration for input line 15 */
#define EXTI_FTSR_FT16_Pos (16U)
#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger configuration for input line 16 */
#define EXTI_FTSR_FT17_Pos (17U)
#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger configuration for input line 17 */
#define EXTI_FTSR_FT18_Pos (18U)
#define EXTI_FTSR_FT18_Msk (0x1UL << EXTI_FTSR_FT18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_FT18 EXTI_FTSR_FT18_Msk /*!< Falling trigger configuration for input line 18 */
#define EXTI_FTSR_FT20_Pos (20U)
#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger configuration for input line 20 */
/****************** Bit definition for EXTI_SWIER register ****************/
#define EXTI_SWIER_SWI0_Pos (0U)
#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWI1_Pos (1U)
#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWI2_Pos (2U)
#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER_SWI3_Pos (3U)
#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER_SWI4_Pos (4U)
#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER_SWI5_Pos (5U)
#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER_SWI6_Pos (6U)
#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER_SWI7_Pos (7U)
#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER_SWI8_Pos (8U)
#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER_SWI9_Pos (9U)
#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER_SWI10_Pos (10U)
#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER_SWI11_Pos (11U)
#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER_SWI12_Pos (12U)
#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER_SWI13_Pos (13U)
#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER_SWI14_Pos (14U)
#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER_SWI15_Pos (15U)
#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWI16_Pos (16U)
#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWI17_Pos (17U)
#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWI18_Pos (18U)
#define EXTI_SWIER_SWI18_Msk (0x1UL << EXTI_SWIER_SWI18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWI18_Msk /*!< Software Interrupt on line 18*/
#define EXTI_SWIER_SWI20_Pos (20U)
#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20*/
/******************* Bit definition for EXTI_PR register ******************/
#define EXTI_PR_PR0_Pos (0U)
#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
#define EXTI_PR_PR1_Pos (1U)
#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
#define EXTI_PR_PR2_Pos (2U)
#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
#define EXTI_PR_PR3_Pos (3U)
#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
#define EXTI_PR_PR_Pos (4U)
#define EXTI_PR_PR_Msk (0x1UL <