155 lines
5.9 KiB
C
155 lines
5.9 KiB
C
/**
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******************************************************************************
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* @file system_py32f040.c
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* @author MCU Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#include "py32f0xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined (LSI_VALUE)
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#define LSI_VALUE 32768U /*!< Value of LSI in Hz*/
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#endif /* LSI_VALUE */
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#if !defined (LSE_VALUE)
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#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/
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#endif /* LSE_VALUE */
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define FORBID_VECT_TAB_MIGRATION */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x100. */
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/******************************************************************************/
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = HSI_VALUE;
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const uint32_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint32_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint32_t HSIFreqTable[8] = {4000000U, 8000000U, 16000000U, 22120000U, 24000000U, 4000000U, 4000000U, 4000000U};
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/**
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* @brief Clock functions.
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* @param none
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* @return none
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*/
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void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
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{
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uint32_t tmp;
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uint32_t hsidiv;
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uint32_t hsifs;
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#if defined(RCC_PLL_SUPPORT)
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uint32_t pllmul=0;
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const uint8_t pllMulValue[4] = {2,3,2,2};
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#endif /* RCC_PLL_SUPPORT */
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_SYSCLKSOURCE_STATUS_LSI: /* LSI used as system clock */
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SystemCoreClock = LSI_VALUE;
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break;
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#if defined(RCC_LSE_SUPPORT)
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case RCC_SYSCLKSOURCE_STATUS_LSE: /* LSE used as system clock */
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SystemCoreClock = LSE_VALUE;
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break;
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#endif /* RCC_LSE_SUPPORT */
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#if defined(RCC_PLL_SUPPORT)
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case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
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pllmul = pllMulValue[((RCC->PLLCFGR & RCC_PLLCFGR_PLLMUL)>>RCC_PLLCFGR_PLLMUL_Pos)] ;
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if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI) /* HSI used as PLL clock source */
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{
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hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos);
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SystemCoreClock = pllmul * (HSIFreqTable[hsifs]);
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}
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else /* HSE used as PLL clock source */
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{
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SystemCoreClock = pllmul * HSE_VALUE;
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}
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break;
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#endif /* RCC_PLL_SUPPORT */
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case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */
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default: /* HSI used as system clock */
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hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos);
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hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
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SystemCoreClock = (HSIFreqTable[hsifs] / hsidiv);
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Setup the microcontroller system.
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* Initialize the System.
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* @param none
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* @return none
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*/
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void SystemInit(void)
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{
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/* Set the HSI clock to 8MHz by default */
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/* Set the LSI clock to 32.768KHz by default */
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RCC->ICSCR = (RCC->ICSCR & 0xFE000000) | (0x1 << 13) | ((*(uint32_t *)(0x1fff3208)) & 0x0000FFFF) | ((*(uint32_t *)(0x1fff3348))<<16);
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif /* VECT_TAB_SRAM */
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}
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/************************ (C) COPYRIGHT Puya *****END OF FILE******************/
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