245 lines
7.4 KiB
C
245 lines
7.4 KiB
C
#ifndef __P11__
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#define __P11__
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//===============================================================================//
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//
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// sfr define
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//
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//===============================================================================//
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#ifdef PMU_SYSTEM
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#define p11_base 0x000000
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#define p11_ram_base p11_base
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#define p11_sfr_base 0x00a000
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#else
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#define p11_base 0xf20000
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#define p11_ram_base p11_base
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#define p11_sfr_base 0xf2a000
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#endif
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#define __RW volatile // read write
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#define __RO volatile const // only read
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#define __WO volatile // only write
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#define __u8 unsigned int // u8 to u32 special for struct
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#define __u16 unsigned int // u16 to u32 special for struct
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#define __u32 unsigned int
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#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
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#define __s16(x) short(x); short(reserved_1_##x)
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#define __s32(x) int(x)
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#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
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#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
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#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
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//===============================================================================//
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//
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// sfr address define
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//
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//===============================================================================//
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//............. 0x0000 - 0x03ff............ for cpu
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// #include ../core/csfr.h
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//............. 0x0400 - 0x04ff............ for clock
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typedef struct {
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__RW __u32 PWR_CON;
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__RW __u32 RST_SRC;
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__RW __u32 WKUP_EN;
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__RW __u32 WKUP_SRC;
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__RW __u32 SYS_DIV;
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__RW __u32 CLK_CON0;
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__RW __u32 CLK_CON1;
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__RW __u32 CLK_CON2;
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__RW __u32 CLK_CON3;
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} P11_CLOCK_TypeDef;
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#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
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#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
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//............. 0x0500 - 0x05ff............ for memory control
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typedef struct {
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__RW __u32 MPC0;
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__RW __u32 MPC1;
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__RW __u32 MSC;
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} P11_MEM_CTL_TypeDef;
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#define P11_MEM_CTL_BASE (p11_sfr_base + map_adr(0x05, 0x00))
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#define P11_MEM_CTL ((P11_MEM_CTL_TypeDef *)P11_MEM_CTL_BASE)
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//............. 0x0600 - 0x06ff............ for system
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typedef struct {
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__RW __u32 P2M_INT_IE;
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__RW __u32 P2M_INT_SET;
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__RW __u32 P2M_INT_CLR;
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__RO __u32 P2M_INT_PND;
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__RW __u32 P2M_CLK_CON0;
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__RW __u32 M2P_INT_IE;
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__RW __u32 M2P_INT_SET;
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__RW __u32 M2P_INT_CLR;
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__RO __u32 M2P_INT_PND;
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__RW __u32 P11_SYS_CON0;
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__RW __u32 P11_SYS_CON1;
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__RW __u32 MEM_PWR_CON;
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} P11_SYSTEM_TypeDef;
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#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
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#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
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//............. 0x0800 - 0x08ff............ for watch dog
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typedef struct {
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__RW __u32 CON;
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__RW __u32 KEY;
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__RW __u32 DUMMY;
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} P11_WDT_TypeDef;
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#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
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#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
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//............. 0x0900 - 0x0cff............ for lp timer
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typedef struct {
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__RW __u32 CON0;
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__RW __u32 CON1;
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__RW __u32 CON2;
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__RW __u32 PRD;
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__RW __u32 RSC;
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__RO __u32 CNT;
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} P11_LPTMR_TypeDef;
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#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
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#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
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#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
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#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
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#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
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#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
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#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
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#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
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//............. 0x0d00 - 0x0dff............ for irflt
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typedef struct {
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__RW __u32 CON;
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} P11_IRFLT_TypeDef;
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#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
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#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
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//............. 0x0e00 - 0x0eff............ for spi
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typedef struct {
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__RW __u32 CON;
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__WO __u32 BAUD;
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__RW __u32 BUF;
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//__WO __u32 ADR;
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//__WO __u32 CNT;
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} P11_SPI_TypeDef;
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#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
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#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
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//............. 0x0f00 - 0x10ff............ for uart
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typedef struct {
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__RW __u16 CON0;
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//__RW __u16 CON1;
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__WO __u16 BAUD;
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__RW __u8 BUF;
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__RW __u32 OTCNT;
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//__RW __u32 TXADR;
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//__WO __u16 TXCNT;
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//__RW __u32 RXSADR;
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//__RW __u32 RXEADR;
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//__RW __u32 RXCNT;
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//__RO __u16 HRXCNT;
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__RW __u16 CON2;
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} P11_UART_TypeDef;
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#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
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#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
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#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
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#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
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//............. 0x1100 - 0x11ff............ for iic
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typedef struct {
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__RW __u32 CON0;
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__RW __u32 CON1;
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__RW __u32 BAUD;
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__RW __u32 BUF;
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} P11_IIC_TypeDef;
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#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
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#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
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//............. 0x1200 - 0x12ff............ for port
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typedef struct {
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__RW __u32 OCH_CON0 ;
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__RW __u32 ICH_CON0 ;
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__RW __u32 P33_PORT ;
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__RW __u32 PB_SEL ;
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__RW __u32 PB_PU ;
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__RW __u32 PB_PD ;
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__RW __u32 PB_DIR ;
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__RW __u32 PB_DIE ;
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__RW __u32 PB_DIEH ;
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__RW __u32 PB_OUT ;
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__RO __u32 PB_IN ;
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} P11_PORT_TypeDef;
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#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
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#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
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//............. 0x1300 - 0x13ff............ for lp ctmu
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typedef struct {
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__RW __u32 CON0;
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__RW __u32 CON1;
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__RW __u32 CON2;
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__RW __u32 CON3;
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__RW __u32 ANA0;
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__RW __u32 ANA1;
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__RW __u32 RES;
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} P11_LPCTM_TypeDef;
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#define P11_LPCTM_BASE (p11_sfr_base + map_adr(0x13, 0x00))
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#define P11_LPCTM ((P11_LPCTM_TypeDef *)P11_LPCTM_BASE)
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//............. 0x1400 - 0x14ff............ for lpvad
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typedef struct {
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__RW __u32 VAD_CON;
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__RW __u32 VAD_ACON0;
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__RW __u32 VAD_ACON1;
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__RW __u32 AVAD_CON;
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__RW __u32 AVAD_DATA;
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__RW __u32 DVAD_CON0;
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__RW __u32 DVAD_CON1;
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__RW __u32 DMA_BADR;
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__RW __u32 DMA_LEN;
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__RW __u32 DMA_HPTR;
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__RW __u32 DMA_SPTR;
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__RW __u32 DMA_SPN;
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__RW __u32 DMA_SHN;
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} P11_LPVAD_TypeDef;
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#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x14, 0x00))
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#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
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//............. 0x1500 - 0x16ff............ for crossbar
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#include "p11_io_omap.h"
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#include "p11_io_imap.h"
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//............. 0x1700 - 0x18ff............ for gp timer
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typedef struct {
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__RW __u32 CON;
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__RW __u32 CNT;
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__RW __u32 PRD;
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__RW __u32 PWM;
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} P11_GPTMR_TypeDef;
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#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x17, 0x00))
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#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x00))
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#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
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#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
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#endif
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